1. Field of the Invention
The present invention relates to a frequency divider and a phase locked loop, and more particularly, to a low power frequency divider and a low power phase locked loop, which consume the least power.
2. Description of the Related Art
A frequency divider performs a function of dividing a frequency of an input signal, and generally includes a counter circuit used to recognize the frequency of the input signal. The counter circuit recognizes the frequency of the input signal by using a plurality of transistors that are turned on or turned off in response to the input signal, and generates a signal by dividing the frequency of the input signal in a uniform ratio according to the recognized frequency.
Since a current is mostly used at a switching moment when a transistor repeats turned on and turned off states, an operation speed of the counter circuit determines power consumption of the frequency divider. The frequency divider is mostly used in a phase locked loop, and since power consumption of the counter circuit constitutes most of the power consumption of the frequency divider, power consumption of the phase locked loop including the frequency divider including the counter circuit having such electric characteristics is also increased.